Design of Communication Module Based on AVR Microcontroller Serial Port to FSK

With the rapid development of information technology and network technology, information interaction application business brings more convenience to human life, and information terminals show great market potential. However, due to different end-user environments, user information interaction may be different. Currently, IP, FSK, and wireless communication methods are commonly used. In order to improve the competitiveness of the terminal market and reduce the investment in system development costs, the independent design of the communication module and the terminal program is an ideal solution. This article uses ATmega48 chip and CMX865 chip to implement FSK communication module. Based on this module, FSK information interaction between user and service platform is simple serial communication with terminal.

1ATmega48 Introduction

The ATmega48 is a high performance, low power 8-bit CMOS microcontroller based on the AVR Enhanced RISC (Reduced Instruction Set) architecture. The microcontroller features a controllable power-on reset and programmable brownout detection circuitry, a calibrated on-chip RC oscillator, 18 on-chip and off-chip interrupt sources, and five sleep modes. Due to its advanced instruction set and single clock cycle instruction execution time, ATmega48's data throughput rate is up to 1MIPs/MHz, which is 10 times faster than ordinary microcontrollers, which can alleviate the contradiction between power consumption and processing speed.

It integrates 4KB of in-system programmable Flash, 256-byte EEPROM, and 512-byte SRAM. Its peripherals have a programmable serial USART interface and an SPI serial interface that can operate in master/slave mode; there are two 8-bit timer/counters with independent prescaler and comparator functions and one with pre- 16-bit timer/counter for divider, compare function and capture function, programmable watchdog timer with independent on-chip oscillator, etc. The ATmega48/88/168 chip hardware circuit can be fully compatible, and the AVR chip can be flexibly selected according to the actual needs of the software, which greatly facilitates the development and development of the system.

Introduction to 2CMX865

The CMX865 is a new DTMF encoder/decoder/FSK modem IC chip from CML that uses a single high-speed serial bus control and is compatible with most serial interfaces. The main features of the CMX865 are:

â—†Power supply voltage 2.7 ~ 5.5V, low power operation mode;

â—†Support V. 23, Bell202FSK1200bps encoding / decoding;

â—† Integrated high reliability DTMF, encoder / decoder;

â—† Integrated ring detection function, support for voice detection.

3 hardware design

Figure 1 shows the serial to FSK communication module circuit. The system mainly uses AVR microcontroller ATmega48 chip and CMX865 modulation/demodulation chip as the hardware architecture. ATmega48 chip uses C-BUS bus to control the CMX865 chip to realize FSK communication. The IRQN terminal of the CMX865 chip is connected to the external interrupt 0 (INT0) of the CPU chip to ensure that the software can receive/send FSK data in an interrupted manner. The CMX865 chip's clock signal, chip select signal, response response data signal, and receive control data signal are respectively connected to the common I/O interface pins of the ATmega48 chip. The CPU can control the CMX865 chip through analog port lines.

FSK

Figure 1 also provides a basic FSK receive/transmit data interface circuit and ringer detection circuit. In the FSK transmission circuit, the purpose of the external resistor at the TXA (15-pin) of the CMX865 chip is to match the AC impedance of the chip interface to the line. In the FSK receiving circuit, the capacitance between the CX865 chip RXAFB (9 pins) and RXAN (10 pins) and the isolation transformer are designed to filter out high frequency noise; by adjusting the two resistors R1 in the receiving circuit The resistance of R2 can change the amplitude of the signal provided by the receiving end to the CMX865 chip. In the ringing detection circuit, IC1 is a photocoupler. When the ringer is not ringing, the phototransistor is turned off, and RING is at a high level. When ringing, the ringing signal is stabilized by capacitive coupling and voltage regulator, and the ringing voltage is made in IC1. The LED emits light and illuminates the base of the phototransistor, causing the phototransistor to turn on, RING is low, and a low-level ringing signal is detected through the ATmega48 pin.

4 software implementation

The ATmega48 chip has 4KB of internal Flash and 512 bytes of on-chip SRAM. Software implementation needs to consider resource allocation issues, especially SRAM usage. Since the program involves serial communication, DTMF communication and FSK communication, it is theoretically necessary to open up six buffers. If so, the size of each buffer obviously does not guarantee the need to reach the actual amount of communication data. Combined with FSK communication characteristics, DTMF data transmission and FSK data transmission cannot occur at the same time, so FSK and DTMF can share the same buffer. Same serial port reception and FSK transmission, serial port transmission and

FSK reception will not happen at the same time, so communication only needs to open two buffers to ensure normal communication of the module, considering the actual business platform data volume, software design in the FSK reception to open up 255 bytes buffer reuse; FSK transmission development 45 byte buffer multiplexing.

4.1 main program implementation process

The communication module main program includes: CPU initialization, CMX865 initialization, initialization chain building, serial communication and FSK communication subroutine. The main program flow is shown in Figure 2. Initialization of the link building is the basis of the normal operation of the module. By initializing the chain-building operation, the information terminal can set the parameters of the communication module according to the line environment and the platform timeout mechanism to ensure the stability of the communication. The communication main flow loop executes three sub-function functions: line state processing function, serial port data analysis and processing function, and link hold function. The line state processing function is designed with three line states, namely initial state, idle state and off-hook state; during normal operation, it only switches between idle state and off-hook state. Among them, the ringing is detected in the idle state, the off-hook is performed according to the status bit, and the DTMF dialing is performed; in the off-hook state, FSK transmission and reception, off-line detection, and on-hook control are performed according to the status bits. The serial port data parsing and processing functions include serial port data parsing by command set, response to parsing commands, and status set processing. Thus, the line state processing function and the serial port data parsing and processing function are closely connected by the state set flag. The FSK data is directly received by the interrupt mode. After receiving the data, it is sent to the information terminal through the serial port in the off-hook state. Since the serial port transmission application is relatively simple, the instant response processing method for the simple processing serial port transmission is dispersed in the sub-function functions of the main communication process, thereby improving the communication efficiency. The link hold function determines whether the serial port communication is abnormal, and the communication module periodically sends a link hold command to the information terminal. If the terminal response command is not received after 3 times of retransmission, the communication module will automatically lock the line and re-execute the initialization. Chain operation to achieve serial port exception handling.

FSK

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