Gigabit Ethernet network transceiver detonates connection port growth trend

Gigabit Ethernet network transceiver detonates connection port growth trend

Ethernet has become the most widely used enterprise communication standard in the world. As most enterprises begin to transfer traditional information systems to the network, the bandwidth usage of the enterprise network has increased significantly every year. In addition, desktop conferences, New technologies such as network virtual meetings and group-oriented productivity applications also keep today's network in peak use.
With the rapid increase in bandwidth demand, switch router equipment manufacturers have begun to develop systems that can be expanded to meet the market's endless requirements for transmission bandwidth. This result is reflected in the number of ports of the switching router. The number of ports of a typical switching router has surged from 8 to 72 ports per system in a short period of time.
Switch router designers are now facing important tests such as increasing connection port density, reducing costs, reducing power consumption, and reducing system size. Multi-port Gigabit Ethernet (MulTI-port Gigabit Ethernet) transceivers are an important development for these issues. This article will discuss in depth the important role of these transceivers in the design of Ethernet switching routers.

Figure 1: Gigabit Ethernet signal chain
Gigabit Ethernet networks can be divided into two major categories. The first type of transceivers are collectively called 1000BaseT transceivers (IEEE 802.3ab compatible Gigabit Ethernet copper physical layer components), and the second type of transceivers are used to drive SFP (Small Form Factor Pluggable) and GBIC (Gigabit Interface Converter) and other optical transceiver circuit transceiver components, these transceivers are usually called Gigabit Ethernet transceivers, or Serdes (compliant with IEEE803.z standard). This article will discuss the second type of transceiver and its significant impact on the cost, power consumption, and size of existing system designs.
Designers must understand that as the number of 10/100 / 1000BaseT ports on the corporate network continues to increase, Gigabit Ethernet uplink ports (uplink ports) will become the main technical bottleneck of routers. Not only do switching routers require more Gigabit Ethernet uplink ports, but network hubs and data centers also require larger Gigabit Ethernet switches.

Figure 2: Evolution of optical network ports Over the past decade, Gigabit Ethernet transceivers that specifically drive optical upstream ports have evolved from single-port components to complex multi-port system-on-a-chip. Figure 3 shows the evolution of Gigabit Ethernet transceivers over the past decade.

Figure 3: System evolution Figure 4 can be used as a reference. It is the growth situation of Gigabit Ethernet optical fiber connection ports and the future growth forecast.

Figure 4: Forecast of the number of Gigabit Ethernet optical connection ports. From the graph in Figure 4, it can be seen that due to the increasing number of 10/100 / 1000BaseT ports, designers of Gigabit Ethernet switching routers must continue to develop new technologies to increase the uplink of Gigabit Ethernet networks. Number of ports.
As product design generations alternate, switch router designers have begun to deal with or solve important issues such as power consumption, cost, and board area; these issues will come back to affect important customers such as product price, scalability, usability, and service capabilities. Claim.

Figure 5: Important design issues and requirements The next focus of this article will be on how to choose Gigabit Ethernet transceivers to achieve system goals, and at the same time solve all the important challenges faced by designers of Gigabit Ethernet switching routers.
Choosing the right transceiver for the application. When selecting a Gigabit Ethernet transceiver, the development of multi-port products may encounter huge power requirements, power consumption, and limited circuit board area. Therefore, switching router developers must consider many factors. When choosing a Gigabit Ethernet transceiver, designers must consider four key areas: interface (parallel and serial), power consumption, packaging, and cost. This article will discuss each of these four areas.
One. interface
1.1 Parallel interface
Gigabit Ethernet transceivers have many interfaces that designers need to consider and select, including parallel data interfaces, high-speed serial interfaces, and control interfaces. The parallel interface of Gigabit Ethernet transceivers has developed quite rapidly recently. In the past many years, because the design and implementation of the 10-bit parallel interface are very simple, it has become the main interface of the Gigabit Ethernet transceiver. The 10-bit interface (Ten-Bit Interface, TBI) evolved from the Gigabit Media Independent Interface (GMII), and GMII was developed by the standards body responsible for managing the Ethernet network specifications.
The TBI / GMII interface uses the LVTTL signal level, and the data is controlled by the rising edge of the reference frequency. The main difference between the GMII interface and the TBI interface is that the GMII interface includes Physical Coding Sub-layer (PCS) functions, and components that support the TBI interface usually do not provide these functions. The key to choosing the TBI or GMII interface is the media access controller (MAC) used, and whether these media access controllers have the required PCS functions built-in, or the transceiver needs to provide these functions.
Over the years, TBI / GMII interfaces have been gradually replaced by reduced bit interfaces. These interfaces will reduce the total number of pins and chip area, while increasing the density of connection ports. The main reason for this change is that designers need to increase the number of connection ports in the system while minimizing the cost of related ASIC and MAC components. Reduced Ten Bit Interface (RTBI) and Reduced Gigabit Media Independent Interface (RGMII) are currently the most widely used streamlined bit interfaces. RTBI is a simplified version of the traditional 10-bit interface. It reduces the width of the original parallel bits from 8/10 bits to 4/5 bits. Bit); the signal bit criteria changed from LVTTL and SSTL2 to HSTL. These 4/5 bits will be controlled by the rising and falling edges of the reference frequency, which means that the reduced bit interface only needs half of the pins to achieve the same actual data rate as the traditional 10 bit interface. Halving the number of pins is a great benefit for systems with 24 or 48 Gigabit Ethernet ports.

Figure 6: Simplified bit interface
RGMII is mainly used as an alternative to TBI / GMII and RTBI. It will use the four control signals to multitask the data at the rising and falling edges of the reference frequency, reducing the maximum number of I / O pins from 23 (the parallel end of the TBI interface) to 12 (including the control pins) .
Designers must carefully plan and understand the signal chain when choosing an interface for their application; this is especially true when designing the MAC / ASIC for the Gigabit Ethernet transceiver interface. If the designer's goal is to increase the number of Gigabit Ethernet connection ports as much as possible, and maintain the system volume unchanged, they should consider using a reduced bit interface (RTBI / RGMII).
Figure 7: Pin description of the reduced bit interface Signal name RTBI RGMII Description
TXC MAC MAC varies with speed, and the transmission reference frequency is 125 MHz, 25 MHz, or 2.5 MHz ± 50 ppm
TD [3: 0] PCS MAC In RTBI mode, it contains bits 3: 0 on the rising edge of TXC and bits 8: 5 on the falling edge. In RGMII mode, it contains bits 3: 0 on the rising edge of TXC and bits 7: 4 on the falling edge
TX_CTL PHY PHY In RTBI mode, it contains bit 5 on the rising edge of TXC and bit 10 on the falling edge. In RGMII mode, it contains TXEN on the rising edge of TXC and the logical differential values ​​of TXEN and TXERR (logical derivaTIve) on the falling edge
RXC PHY PHY continuous reception reference frequency is 125 MHz, 25 MHz or 2.5 MHz ± 50 ppm, and is generated from the data stream received from it
RD [3: 0] PHY PHY In RTBI mode, it contains bits 3: 0 on the rising edge of RXC and bits 8: 5 on the falling edge. In RGMII mode, it contains bits 3: 0 on the rising edge of RXC and bits 7: 4 on the falling edge
RX_CTL PHY PHY In RTBI mode, it contains bit 5 on the rising edge of RXC and bit 10 on the falling edge. In RGMII mode, it contains RXDV on the rising edge of RXC and the differential value of RXDV and RXERR on the falling edge
1.2 Serial interface
The high-speed serial interfaces currently provided by Gigabit Ethernet transceivers can be divided into three signal levels (logic level, LVPECL (Low Voltage Pseudo Emitter Coupled Logic), CML (Current Mode Logic), and VML (Voltage Mode Logic) Please refer to Figure 8 for comparison. The choice of the serial interface used to be determined by the type of optical module connected to the transceiver; the current design uses AC-coupled SFP optical modules. This consideration is no longer as important as factors such as I / O power supply capability or terminal matching. For example, Texas Instruments ’new transceiver uses VML technology with built-in terminal matching. The VML driver is fully compatible with LVPECL signals as long as it uses AC coupling.
VML driver components use CMOS process technology, which has the advantage that it does not require external boost resistors, because the NMOS and PMOS transistor architectures used by them can simultaneously drive falling / rising signal edges.
Rated voltage parameter parameters of different logic levels LVPECL CML VML LVDS
VOH 2.4 V 1.9 V 1.65 V 1.4 V
VOL 1.6 V 1.1 V 0.85 V 1 V
Output voltage (single-ended) 800 mV 800 mV 800 mV 400 mV
Common mode voltage 2 V 1.5 V 1.25 V 1.2 V

Figure 8: The main factors that should be considered when selecting the correct serial interface for the logic level of the serial I / O:
-Overall impact on power consumption
-Overall impact on implementation
-Interoperability with optical modules and circuit modules
1.3 Control interface As the connection ports of the chip continue to increase, the control interface has also evolved from independent I / O pins on each port to a reliable serial communication bus. The serial communication bus of the Ethernet network is also known as Management Data Input Output (MDIO), which is defined by IEEE according to various contents of the Ethernet standard IEEE802.3 (Article 22). MDIO is a simple two-wire serial interface that connects management components such as microprocessors to transceivers that support management functions (such as multi-port Gigabit Ethernet transceivers or 10GbE XAUI transceivers) to control reception And collect status information from the transceiver. The information that MDIO can collect includes:
-Link status
-Speed ​​ability and choice
-Power saving sleep state
-TX / RX mode selection
-Auto negotiation control
-Loop mode control
-Other functions In addition to the functions required by IEEE, transceiver manufacturers can also add other information collection functions.

Figure 9: MDIO application example When designers choose Gigabit Ethernet transceivers, it is best to choose the built-in MDIO components, and do not consider products that do not provide this powerful control interface.
two. Power consumption Power consumption is another important consideration when choosing a Gigabit Ethernet transceiver. Almost all modern electronic devices attach great importance to power consumption. For Ethernet switches and routers, it has become a major consideration for the dense design of many ports. Although the density of Gigabit Ethernet connection ports continues to increase, as long as the product size remains unchanged, its power budget will usually remain fixed. Basically, designers must squeeze more ports into a single chassis, and ensure that the total power consumption does not change, or only slightly increases. The new Gigabit Ethernet transceiver has been able to help designers solve some of this problem. In the past five years, the chip manufacturing process used in Gigabit Ethernet transceivers has shifted from BiCMOS / BiPolar to low-power CMOS technology, reducing the power consumption of each port from 1 W to less than 200 mW.

Figure 10: Power consumption reduction curve. When choosing a Gigabit Ethernet transceiver, a useful rule of thumb is to choose CMOS process products; the individual channel power consumption of such components is about 200 mW to 300 mW. Advances in process technology have reduced the voltage required by the components. Most components can currently use 2.5 V or 1.8 V power supplies.
3. Packaging Most of the multi-channel transceivers are currently packaged in large PBGA packages with a pin pitch from 1 cm to 0.8 cm. Figure 11 shows the difference between multi-channel and single-channel components.

Figure 11: Area comparison of multi-channel and single-channel components. Packaging has a great influence on the number of ports that the design can provide. In the case of Gigabit Ethernet transceivers, designers must use a large BGA package that supports DDR parallel channel mode (as mentioned earlier) to achieve the design goals. The choice of packaging should be considered together with the circuit board design restrictions and the overall system architecture; for example, although the BGA package can reduce the size of the component, when it is reduced to a certain extent, the implementation cost will far exceed the increase in the number of ports Benefits. As the number of channels increases, components have to adopt more complicated and troublesome interface modes, so today's Gigabit Ethernet transceivers will make an appropriate choice between these factors.
When choosing today's multi-channel Gigabit Ethernet transceiver, it is best to choose less than 300 pins (depending on the number of connection ports supported by the component), the pin spacing is about 1 cm, and the component area is less than 20 × 20 cm BGA package.
4. Cost Cost per port is an important factor that designers care about when comparing Gigabit Ethernet transceivers provided by different manufacturers. The new Gigabit Ethernet transceivers are mostly developed with CMOS process technology optimized for cost. In addition, advances in packaging technology and fierce competition in the packaging foundry market have also brought more cost-competitive solutions to the market. Today, Gigabit Ethernet transceivers cost about US $ 2.50 to US $ 1.50 per port for mass production.
Other factors that directly affect costs include implementation costs (external parts), power management requirements, and thermal management requirements (heat sinks and fans, etc.). In addition to this, the choice of transceivers usually takes into consideration the development goals of ASIC / FPGA / MAC. Therefore, engineers should not only consider the cost of Gigabit Ethernet transceivers, but should consider the cost of the entire design (ASIC and transceiver) as a decision factor.
When choosing a Gigabit Ethernet transceiver, the designer must take the entire signal chain into consideration and at the same time consider the main design goals as an important reference for part selection.
Select the checklist:
1. Interface
-ASIC / FPGA selection and development
-Selection and implementation of timing parts
-Control mechanism
2. Power supply:
-Power plane design
-Thermal management
3. Packaging:
-Circuit board design
-Circuit board layout
4. Cost:
-Overall system feasibility
-Implementation cost
-In terms of performance, all Gigabit Ethernet transceivers must meet IEEE requirements in order to become a qualified Gigabit Ethernet (IEEE802.3z) transceiver. But it is still not enough to compete in today's market only if the performance meets the standard; designers must find out other factors that have the greatest impact on their design, such as power consumption, volume, and cost.
Designers can analyze applications that require multiple Gigabit Ethernet connection ports to understand the impact of using new multi-channel Gigabit Ethernet transceivers in their designs. Here we take the 24-port Gigabit Ethernet switching router as an example, and then compare the impact of a single-channel Gigabit Ethernet transceiver and multi-channel components.
TLK2208A in TI mass production and TLK2226 in sample supply are the two best examples of multi-channel Gigabit Ethernet transceivers. The important parameters of the two transceiver components are shown in the following table:



Number of channels



Side by side interface












Package size

19 × 19 cm

15 × 15 cm

Total power consumption

1.2 W

1 W

Figure 12: Important parameters of components

In this example of a switching router, we chose TLK2208B as the target design transceiver; its main consideration is to save board area and reduce power consumption, and minimize the number of pins on the ASIC interface. To implement the 24-port solution, we use three TLK2208Bs to support all 24 ports; in contrast, if this design uses the previous single-channel Gigabit Ethernet transceiver components, the entire solution requires 24 transceivers. As can be seen from the figure below, the use of multi-channel Gigabit Ethernet transceivers to implement this solution can indeed save considerable circuit board area.

Figure 13: Circuit board area comparison In this example, using an eight-channel TLK2208B transceiver can save up to 1,300 square centimeters of circuit board area. In addition, the single-channel solution may also require larger component spacing and winding area, which will increase its total board area.
Most of the large multi-channel components use the new CMOS process technology, and the working efficiency of the architecture is also higher than the previous products, so the new Gigabit Ethernet transceiver design naturally has an advantage in power consumption. For example, the power consumption of each channel of TLK2208B is about 165 mW, and the traditional single-channel components are from 250 mW to 600 mW (depending on the technology); this means that compared to traditional single-channel transceivers, components such as TLK2208B can The consumption is reduced by 35% to 75%.
Because the TLK2208B uses a reduced bit interface with a rising edge and a falling edge as the frequency, a shared MDIO control bus, and a single reference frequency input, its interface with MAC / ASIC is simpler and lower cost than a single channel solution. . If product development includes the design of new ASIC components, then selecting components like TLK2208B may be the only cost-effective ASIC implementation solution. Figure 14 is a comparison of the number of pins implemented using single-channel and multi-channel components.

Use components

Number of pins in the solution

3 TLK2208B

867 pins

24 single-channel transceivers with 64 pins

1536 pins

Figure 14: Comparison of pin counts As can be seen from Figure 14, as long as today ’s multi-channel Gigabit Ethernet transceivers are used, designers can develop systems with more connection ports and meet less power consumption, lower cost, and Smaller size and other requirements. In many cases, the savings of multi-channel components are indeed considerable.
Based on the aforementioned various examples, we can clearly see that the design of today's multi-port Gigabit Ethernet switches and routers is not easy. This is especially true of successful data communications products because they have many variables to consider; one of them is the Gigabit Ethernet transceiver that drives the Gigabit Ethernet optical link. As long as the new multi-channel Gigabit Ethernet transceiver components such as TI's TLK2208B and TLK2226 are selected, designers can:
-Reduce total system power consumption
-Reduce the total circuit board area
-Reduce the number of I / O pins
-Reduce ASIC interface complexity
-To reduce the overall implementation risk, system manufacturers can use these advantages to develop more reliable and cost-competitive designs to ensure that their products are more widely accepted and set a more brilliant success record in the market. With the continuous advancement of semiconductor technology and the increasing number of system connection ports, Gigabit Ethernet transceiver components will become an important help for design engineers to promote the rapid growth of Gigabit Ethernet connection ports.

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